| For high speed multiplier implementation, the recursive architecture is a parallel and modular approach with low complexity. However, compared to the traditional array multiplier, it costs more area due to the interconnection between modules. The multiplexer based multiplier is adopted as the lower-level multiplier in the proposed architecture because it outperforms the traditional array multiplier in terms of speed, area, and power consumption. To further improve the speed performance, the proposed architecture exploits the carry-select adder (CSA) for partial products addition. The design is synthesized using TSMC 0.18μm standard cell process. According to the experimental results, the proposed hybrid system is superior to the recursive multiplier and the optimized multiplexer based multiplier. Compared with the conventional array multiplier, the propagation delay is reduced by 40% approximately. |
